New ADC from Analog Devices

wb4jfi wb4jfi at
Tue Oct 26 23:28:25 CDT 2010

There's been some discussion over on the openHPSDR group about this for 
the last few days.  It looks very interesting, I hope the price does 
come down some, once it gets used in designs.  I see that they will also 
have an eval board, $300 in 100-qty.  It would be really fun to get an 
eval board, and play with this puppy!  I hope that actual prices are not 
much more than the 100-qty, but they are usually at least twice as much 
for single units.

Using an Si570 (LVDS version) for the clock, or possibly the recommended 
ADC part, plus the recommended ADC front-end chip would be nice, I hope 
one or both parts are on the eval board.

Playing with one of these, followed by either an FPGA board, or 
Beagle/devkit8000, etc could be a huge leap forward.

Thanks Mike.

On 10/26/2010 8:54 PM, Mike O'Dell wrote:
> The bright lads at AD have a new ADC, the AD9467,
> that does 16-bit conversion at 250MSamples/sec
> the spurious-free dynamic range is 100dBF
> and the SNR is 76.4dBFS
> input amp bandwidth is 300MHz with a 2.5Vp-p input
> the gain is programmable so one can trade the various
> specs against each other as the design requires
> amazingly, this puppy only draws 1.35W (needs 1.8 & 3.3 VDC)
> 10mm X 10mm 72pin lead-frame chip-scale package
> the 250MSample/sec version goes for $120
> the 200MSample/sec speed bin goes for $100
> (qty 1000 prices as usual)
> samples now, volume in November
> software, eval boards, etc, as usual from AD
> yes, it's a bit pricey, but not dramatically more than what's
> in the QS-1R. even better, the price will only go one way
> while they work on the next performance bump.
> Something like the QS-1R with one of these gets FM Broadcast directly 
> Twin interleaved ADCs could get 2m & 220MHz bands without sub-sampling
> Quad ADCs could go to 500MHz without sub-sampling
> this is starting to get very interesting. (grin)
>     -mo
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